I would like to know the difference in terms of hardware and software?
Verilog and vhdl are Hardware Description language that are used to write programs for electronic chips .
These language are used in electronic devices that do not share computers basics architecture .
Vhdl is the older of the two and is based on Ada and Pascal , thus inheriting characteristics from both languages .
Verilog is relatively recent and follows the coding methods of c programming language.
VHDL is strongly typed language and scripts that are not strongly typed are unable compile . A strongly typed language like vhdl does not allow the intermixing or operation of variables with different classes . verilog uses week typing ,which is the opposite of strongly typed language.
Another difference is the case sensitivity.Verilog is case sensitive, and would not recognise a variable if the case used is not consistent with what it was previously . on the other hand, VHDL is not case sensitive .
- Verilog is based on C , while VHDL is based on Pascal and Ada .
- Unlike Verilog, VHDL is strongly typed
- Unlike Vhdl , Verilog is case sensitive .
- Verilog is easier to learn compared to VHDL .
- Verilog has very simple data types , while VHDL allows users to create more complex data types .
- Verilog lacks the library management ,like that of VHDL .
Hi…both languages are equally powerful when used to implement FPGA designs.
VHDL has an edge when used for design simulation and verification, as it is a richer language.
I find Verilog like Perl - very terse with a lot of stuff happening implicitly. Or maybe C in the pre-ANSI C days.
I find VHDL much more structured, with everything being far more explicit. Because of this it gives you stubby fingers from typing too much.
I you know C, you will find the syntax of Verilog quite familiar, so much that your head will hurt with the confusion.
The choice is also somewhat country dependant, so maybe see what is used locally by looking at a few job ads.